This disclosure is related to adjusting the timing of data transitions on a parallel interface in relation to a data strobe signal within a computing platform.
As interfaces between components in computing platforms and/or between units within integrated circuits increase in transmission speed and/or bus width, noise and signal integrity issues increase in importance. For some computing platforms, data transfer interfaces may include data that is latched at a receiving device or unit in response to rising and/or falling edges of a clock signal or a data strobe signal generated either by a transmitting device or generated within the receiving device by dividing the clock signal. In response to increased data transfer rates, calibration operations may be performed by some systems to compensate for timing differences between the data signals and one or more data strobe or clock signals. Timing differences may vary over time as a result of variations in voltage and/or temperature.